Routing Congestion in VLSI Circuits: Estimation and Optimization di Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar edito da SPRINGER NATURE
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Routing Congestion in VLSI Circuits: Estimation and Optimization

Estimation and Optimization

EAN:

9780387300375

ISBN:

0387300376

Pagine:
248
Formato:
Hardback
Lingua:
Inglese
Acquistabile con la

Descrizione Routing Congestion in VLSI Circuits: Estimation and Optimization

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.

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